The present invention generally relates to data communication field, and more specifically, to decoding method, decoding apparatus and decoder for correcting burst errors.
Recently, with the continual increasing of data transferring rate in communication and networking areas such as high-speed SERDES etc, forward error correction (FEC) tech based on burst error correction cyclic codes is gaining more and more widespread application.
For example, IEEE 802.3ap standard calls for shortened cyclic codes (2112, 2080) capable of correcting burst error of up to 11-bits, wherein 2080 bits are information bits and the remaining 32 bits are parity bits. Typically, the burst error correction codes includes Fire Code, with the generation polynomial g(x)=(x2L−1+1) p(x). Where all of the Galois field arithmetic is performed in GF(2m), where m is the order of the primitive polynomial p(x) and L is a positive integer such that L<=m and 2L−1 is not divisible by the period of p(x).
At encoder side, by employing linear sequential circuits, the encoding computation can be implemented by using t(x)=b(x)+xn−ku(x), where t(x) is the transmitted encoded data, u(x) is information bits and b(x)=xn−ku(x) mod g(x). Where n is the length of encoded data, k is the length of information bits, and n−k is the length of parity bits.
At decoder side, the decoder generally decodes cyclic codes by the following method.
First, syndrome is generated. For example, the syndrome may be generated by using s(x)=r(x) mod g(x), wherein r(x) is the received code word, and r(x)=t(x)+e(x). Where e(x) is the errors contained in the received data. In particular, when generating syndrome, it is required that the received data is stored into data buffer. Not until the entire frame is received, the syndrome can be generated. It brings about one frame decoding latency for syndrome generation.
Next, the syndrome is detected and is tested for corresponding error pattern. The relationship between the syndrome and error pattern is as below:s(x)=r(x)mod g(x)={t(x)+e(x)} mod G(x)=e(x)mod G(x)
If e(x) is gotten, corrected data will be denoted as c(x)=r(x)+e(x).
Finally, after the frame is decoded, the decoder will send the data with a flag indicating correctable or uncorrectable to upper layer. In IEEE802.3ap standard, if it is determined that the current frame is uncorrectable, FEC layer will modify the related sync head of 64B/66B block, e.g., by adding a flag indicating that the error is uncorrectable, such that the upper PCS layer will know that the ongoing frame is corrupted, and then take corresponding reactions. Thus, it's also very important to determine whether the frame is correctable or uncorrectable immediately before sending the data to upper layers.
In prior art, based on different ways to get e(x), many branches of error decoding scheme is developed. A decoding schema, such as Meggitt decoder, requires that not until the error pattern of the entire frame is determined, the correctability of error can be determined. Then the frame is further processed based on the error pattern and whether the frame is correctable. However, the error pattern determining procedure will introduce about one frame latency. Thus, if one wants to determine whether the frame is correctable or uncorrectable before sending it to the upper layer, it requires two frame decoding latency from the reception of the data. Moreover, it further requires a bigger buffer to store 2 complete frames of data.
Another decoder is designed based on Fire Code. Typical Fire Code decoder can be found on book “Error-Correcting Codes”, published by MIT press in 1972. Generally, the decoding scheme based on Fire Code requires relatively higher computation capability for receiver, and the decoding latency of using said decoding scheme will generally be more than one frame, the exact latency is related to the period of primitive polynomial p(x).
Thus, a decoding schema that overcomes the above problems of the prior art is needed.